The present invention relates generally to communication systems; and, more particularly, to an improved method and apparatus for decoding serially concatenated block- and convolutional-coded data.
Wireless communication systems are often limited in terms of transmitter power and spectrum availability. Broadband communication services often must fit within a limited if narrowband spectrum on an air interface network. Additionally, wireless transmission is significantly more error prone than broadband hard-wired networks. This tends to further reduce data capacity due to the necessity to transmit and process error control protocols.
For these and, other reasons, it is often a goal of digital communications design to maximize the transmission bit rate R and minimize the probability of bit error, or Bit Error Rate (BER) and system power S. The minimum bandwidth (BW) required to transmit at rate (R) is known to be Rs/2, where Rs is the symbol rate. A limit on the transmission rate, called the system capacity, is based on the channel BW and the signal to noise ratio (SNR). This limit theorem, also called the Shannon Noisy Channel Coding Theorem, states that every channel has a channel capacity C which is given by the formula, C=BW log2 (1+SNR), and that for any rate R less than C, there exist codes of rate Rc which can have an arbitrarily small decoding BER.
For some time, the digital communications art has sought a coding/decoding algorithm which would reach the Shannon limit. Recently, coding/decoding schemes, called xe2x80x9cTurbo Codes,xe2x80x9d have been determined to achieve fairly reliable data communication at an SNR which is very close to the Shannon Limit.
One form of turbo decoding operates upon serial concatenated codes. As an example, a serial concatenation of an outer, block codexe2x80x94such as a Reed Solomon codexe2x80x94and an inner, convolutional code, can be found in many communications and data storage applications requiring very low bit error rates. This type of serial concatenation is used, for example, in DBS (Direct Broadcast Satellite) standards.
One such serial concatenated system 100 is illustrated in FIG. 1. The serial concatenated system 100 includes a transmitter portion 102 for communicating encoded information to a receiver portion 104 via a communication channel 106. The transmitter portion 102 uses an outer code encoder or block encoder 108 (e.g., a Reed-Solomon encoder) to encode input bits. The output of the outer code encoder 108 is then provided to an interleaver 110 wherein the signal is shuffled in a predetermined manner. Next, the output of the interleaver is provided to an inner code encoder (e.g., convolutional encoder) 112. The output of the inner code encoder 112 is then modulated by modulator 114 and transmitted over the communication channel 106 to the receiver portion 104 for decoding and processing.
Once demodulated by demodulator 116, the classical approach for decoding a serial concatenated system 100 is to apply a soft-decision inner code decoder (e.g., Viterbi decoder) 118 that receives as inputs soft symbols and outputs hard bit estimates for the inner block code. The outputs of the inner code decoder 118 are then byte-deinterleaved by deinterleaver 120 and provided to an outer code decoder 122 (generally a block decoder such as a Reed-Solomon decoder) that can correct multiple byte errors in a block. If the outer code decoder 122 indicates that the number of errors is beyond its correction capability, it may indicate so and no corrections are made.
In effect, this classical approach to concatenated decoding decomposes the task into two independent procedures: one for the inner code, and another for the outer code. An xe2x80x9coptimalxe2x80x9d decoder is then selected and applied for each of these procedures. However, although each decoder may be optimal for its specific task, the overall composite system may not be optimal for a given concatenated code. This is because (1) the Reed-Solomon decoder uses hardxe2x80x94rather than soft-decision data, and (2) the Viterbi decoder performance could be improved in a second pass decoding operation. In particular, error bursts, which are observed in the first-pass decoding, could be broken up by using the bit decisions from blocks which were successfully decoded by a Reed-Solomon decoder. This operation would, in turn, impact a second-pass Reed-Solomon decoding of the data, perhaps enabling the Reed-Solomon decoder to correct another block that previously was considered uncorrectable. In principle, the sharing of outer-to-inner code decoding information could be re-iterated, resulting in even further improvements. In fact, this technique is similar to turbo decoding in a parallel or serial concatenated code context, with bit-by-bit maximum a posteriori probability (MAP) decoding.
Various iterative (turbo-like) decoding approaches have been used in simulation to decode serial concatenations of convolutional and Reed-Solomon codes. One problem in such decoding processes is determining how the Viterbi algorithm is to be modified to accommodate inputs from Reed-Solomon decoded blocks that are correct. No known technique has been developed for efficiently forcing a Viterbi encoder to constrain certain locations in a data record to desired output logic levels.
Briefly, the present invention uses a pipelined process to accelerate signal decoding and improve receiver performance in a serial concatenated coding environment. As compared with a conventional non-pipelined approach, the resulting coding gain is substantially greater with a decrease in BER. A system according to the present invention is particularly applicable to DBS communications and like applications.
In a disclosed embodiment of the present invention, demodulated serial concatenated data is provided to a first decoder (e.g., a convolutional or Trellis Coded Modulation (TCM) decoder). The decoder output is then deinterleaved and decoded by a second decoder (e.g., an algebraic and/or block decoder). In addition to providing decoded data, the outer decoder also provides at least one decode status signal indicative of the success of second decoder operations. Both the decoder data and decode status signals are provided as inputs to a pipeline decoder unit.
The pipeline decoder unit interleaves the data outputs of the second decoder, as well as the decode status signals. Interleaved data signals are then convolutionally encoded with the same type of convolutional encoder that was used to generate encoded data at the transmitter. The resulting binary xe2x80x9chard-decisionxe2x80x9d data may then be mapped into highly reliable soft-decision data. In one embodiment, for example, a logic level xe2x80x9c0xe2x80x9d may be mapped to a minimum-scale soft-decision value (e.g., 0000 with 4-bit quantization), and a logic level xe2x80x9c1xe2x80x9d mapped to a maximum-scale soft-decision value (e.g., 1111 with 4-bit quantization). In this embodiment, the output of the convolutional encoder 216 (FIG. 2) is not punctured regardless of whether the convolutionally encoded data at the transmitter was punctured. Instead, the xe2x80x9cmappedxe2x80x9d datastream is time-aligned with a buffered version of the original demodulated soft-symbol input sequence (with erasures inserted at punctured locations), and these datastreams are provided to the parallel inputs of multiplexing circuitry. The multiplexing circuitry is responsive to the interleaved decode status signals to selectively provide data to a third decoder.
In an exemplary embodiment of the invention, the third decoder is a Viterbi decoder configured to function in a similar manner to a MAP sequence decoder when provided with high-reliability hard-decision data from successfully decoded Reed-Solomon blocks. More particularly, when a xe2x80x9cmappedxe2x80x9d data element from a successfully decoded Reed-Solomon block is available, the multiplexing circuitry passes that data to the third decoder. When the incumbent xe2x80x9cmappedxe2x80x9d data element is from a failed Reed-Solomon block, then the multiplexer passes the buffered soft-decision input to the third decoder. Performing a second pass of Viterbi decoding results in a much smaller bit error rate than seen with a first Viterbi decoding pass, in that the third decoder benefits from the entire concatenated coding gain of the first decoding pass. Employing additional pipelined decoding units/operations provides even further improvements in bit error rates.
In an alternate embodiment of the invention, the third decoder is a Viterbi decoder having rescaled path metrics. In this embodiment, the interleaved data outputs of the second decoder are passed directly to the third decoder as forced a-priori values. The interleaved decode status signals are also provided to the third decoder to selectively constrain the output of the third decoder to be based on either the forced a-priori values or a delayed version of the demodulated serially concatenated code data.
A decoder according to the present invention thus provides improved decoding performance as compared to prior solutions, and is suitable for VLSI implementation and operation at relatively high data rates. In addition, with the disclosed pipelined approach, the processing speed of elements in the pipelined data path may be no different from those found in a classical concatenated decoder. Moreover, the present invention does not require a change to existing standards, and provides enhanced performance for communication systems that employ punctured encoding schemes.